一种硬件开销低的电路延时故障检测方法

A Lower Hardware Overhead Method for Delay Fault Detection of Circuits

文章提出一种统一延时测试架构,通过重用在线延时故障检测设计资源实现离线延时检测;首先,提出了一种硬件开销较小的稳定性检测器,对每个关键组合输出的稳定性扰乱因子进行检测;然后通过在稳定性检测器中共享全局误差生成器,可生成各个稳定性检测器的全局误差信号,以表示是否存在延时故障;最后,在扫描链中集成了基于本地扫描的生成器,以支持基于扫描的离线延时检测;仿真实验结果表明,与以前技术相比,文章方法的硬件开销和设计复杂度更低。

This paper proposes a unified delay test architecture, in which the design resources for on--line delay fault detection can be re used to support off--line delay testing. Firstly, a stability checker, which has low hardware overhead, is presented to monitor the stability violation from each critical combinational output. Secondly, a global error generator, which is shared among stability checkers, can produce a global error signal from individual stability checkers to indicate whether a delay fault appears. Finally, a local scan enable generator is incor- porated into the scan chain to support scan--based off--line delay testing. The simulation experimental results show that, Compared to the previous techniques, the proposed delay fault detection methods have much lower hardware overhead and design complexity.