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基于CNFET的低功耗三值门电路设计 被引量:5

Design of Low Power Ternary CNFET Gate Circuit
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摘要 通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出一种基于CNFET的低功耗三值门电路设计方案.该方案在分析CNFET结构及其不同尺寸的碳纳米管对应于不同阈值电压特性的基础上,以多值逻辑理论为指导,设计基于CNFET的三值反相器、与非门、或非门等单元门电路,最后利用HSPICE对所设计的电路进行仿真.结果表明:所设计电路具有正确的逻辑功能,与传统三值门电路相比,三值CNFET门电路平均传输速度提高52.7%,平均能耗节省54.9%. By investigating the Carbon Nanotube Field Effect Transistor (CNFET), this paper proposes a design scheme of low power ternary CNFET gate circuit. The structure of CNFET and the various size of carbon nanotubes corresponding to the different threshold voltages are first analyzed, followed by designing ternary inverter, NAND gate, NOR gate and other unit gate circuit, all of which are implemented on the basis of multi-valued logic theory. Finally, HSPICE is used to simulate the circuit design. The results show that the designed circuits have expected logic functionality. Comparing with the traditional ternary gate circuit, the transmission speed of CNFET gate circuit increases on average by 52.7%, and energy is saved by 54.9%.
出处 《宁波大学学报(理工版)》 CAS 2014年第3期43-49,共7页 Journal of Ningbo University:Natural Science and Engineering Edition
基金 国家自然科学基金(61234002) 浙江省自然科学基金(Z1111219)
关键词 低功耗 碳纳米场效应晶体管 多值逻辑 门电路 low power consumption carbon nanotube field effect transistor multi-valued logic gate circuit
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参考文献12

  • 1Vasundara P K S, Gurumurthy K S. Quaternary CMOS combinational logic circuits[C]. International Conference on Information and Multimedia Technology, 2009:538- 542.
  • 2汪鹏君,梅凤娜.三值绝热JKL触发器的设计[J].北京科技大学学报,2012,34(12):1464-1468. 被引量:1
  • 3吴训威.多值逻辑电路设计原理[M].杭州:杭州大学出版社,2000.
  • 4Nepal K. Dynamic circuits for ternary computation in carbon nanotube based field effect transistors[C]. 8th IEEE International Conference on NEWCAS, 2010:53- 56.
  • 5王耀.碳纳米管场效应管及其应用电路的建模分析[D].长沙:国防科学技术大学,2008.
  • 6Deng Jie, Wong H S E A Compact spice model for carbon-nanotube field-effect transistors including non- idealities and its application part I: Model of the intrinsic channel region[J]. IEEE Transactions on Electron Devices, 2012, 12(54):3186-3194.
  • 7Biswas S, Jameel K M, Haque R, et al. A novel design and simulation of a compact and ultra fast CNTFET multi-valued inverter using HSPICE[C]. 14th Interna-tional Conference on UK Sim, 2012:671-677.
  • 8Nan H, Ken C. Novel ternary logic design based on CNFET[C]. SOC Design Conference, 2010:115-118.
  • 9Vudadha C, Saiphaneendra P, Sreehari V, et al. CNFET based ternary magnitude comparator[C]. International Symposium on Communications and Information Tech- nologies (ISCIT), 2012:942-946.
  • 10Lin Sheng, Kim Y B, Lombardi F. A novel Cntfet-based ternary logic gate design[C]. IEEE International Midwest Symposium on Circuits and Systems Conference, 2009: 435-438.

二级参考文献11

  • 1Phyu M W, Fu K, Goh W L, et al. Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Trans Very Large Scale Integr VLSI Syst, 2011, 19( 1 ) : 1.
  • 2Zhao X H, Guo J K, Song G H. An improved low-power clock-gating pulse-triggered JK flip-flop // Proceedings of International Conference on Information, Networking and Automation. Kunruing, 2010:2489.
  • 3Inaba M, Tanno K, Tamura H, et al. Optimization and verification of current-mode multiple-valued digit orns arithmetic circuits. IEICE Trans InfSyst, 2010, E93-D(8) : 2073.
  • 4Calabrese F, Celentano G. Embedded multivalued control for ceramic manufacturing. IEEE Trans Ind Electron, 2011, 58 ( 3 ) : 761.
  • 5Anuar N, Takahashi Y, Sekine T. Two phase clocked adiabatic static CMOS logic and its logic family. J Semicond Technol Sci, 2010, 10(1): 1.
  • 6Lu J, Liu H, Ye M, et al. An energy recovery D flip-flop for low power semi-custom ASIC design//Proceedings of the 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. Shartghai, 2010:33.
  • 7Wang P J, Li K P, Mei F N. Design ofa DTCTGAL circuit and its application. J Semicond, 2009, 30 ( 11 ) : article No. 115005.
  • 8杭国强,应时彦.新型电流型CMOS四值边沿触发器设计[J].浙江大学学报(工学版),2009,43(11):1970-1974. 被引量:10
  • 9曾小旁,汪鹏君.时钟低摆幅三值双边沿低功耗触发器的设计[J].华东理工大学学报(自然科学版),2010,36(2):279-283. 被引量:4
  • 10李昆鹏,汪鹏君.三值绝热门控串行数值比较器设计[J].浙江大学学报(理学版),2010,37(4):432-437. 被引量:1

共引文献2

同被引文献25

  • 1吴学祥,沈继忠.用于显性脉冲式触发器的新型低功耗脉冲信号发生器[J].浙江大学学报(理学版),2012,39(4):396-401. 被引量:2
  • 2杭国强.低功耗三值双边沿触发器设计[J].电路与系统学报,2007,12(4):15-19. 被引量:6
  • 3吴训威,陈偕雄.具有三轨输出的三值触发器及其在三值时序电路中的应用[J].中国科学,1985(7):643-654.
  • 4DENG JIE, WONG H S E A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application part I: Model of the intrinsic channel region[J]. IEEE Transactions on Electron Devices, 2012, 54(12):3186-3194.
  • 5BISWAS S, JAMEEL K M, HAQUE R, et al. A noveldesign and simulation of a compact and ultra fast CNTFET multi-valued inverter using HSPICE[C]//2012 14th International Conference on Modelling and Simulation, IEEE Computer Society. Cambridge: IEEE, 2012:671-677.
  • 6NAN H, CHOI K. Novel ternary logic design based on CNFET[C]//SoC Design Conference (ISOCC), 2010 International. Seoul: IEEE, 2010:115-118.
  • 7SRINIVASAN P,BHAT A S,MUROTIYA S L,et al.Design and performance evaluation of a low transistor ternary CNTFET SRAM cell[C].2015 International Conference on IEEE Electronic Design,Computer Networks&Automated Verification(EDCAV),2015:39-43.
  • 8LIN S,KIM Y B,LOMBARDI F.CNTFET-based design of ternary logic gates and arithmetic circuits[J].IEEE Transaction on Nanotechnology.2011,10(2):217-225.
  • 9DENG J,WONG H S P.A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and Its application-part I:model of the intrinsic channel region[J].IEEE Transactions on Electron Devices,2007,54(12):3186-3194.
  • 10Stanford Nanoelectronics Lab.Stanford CNFET model and Schottky barrier CNFET model[EB/OL].[2015-12-18].http://nano.stanford.edu/model.php?id=23.

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