摘要
设计了基于FPGA的图像实时处理系统,利用FPGA中IP核的内置缓存模块,通过乒乓结构读写,实现了图像数据在FPGA内部的缓存和提取。同时利用FPGA数据并行处理的特点,实现了图像的二值化和边缘提取等预处理,将图像预处理的时间由原来在DSP内的1s缩小到50ms以内,使实时图像处理成为可能。
The proposed design uses IP core of memory controllers and Ping-pong structure to realize the real-time image data storage and extraction.The design also realizes the image preprocessing such as binarization and edge extraction through data parallel processing in FPGA.System simulation and test results show that the image pre-processing time can be shorten from 1s in DSP to less than 50ms.
出处
《半导体光电》
CAS
CSCD
北大核心
2014年第3期563-566,共4页
Semiconductor Optoelectronics