0.18 μm CMOS高集成度可编程分频器的设计

Design of 0.18 μm CMOS Highly Integrated Programmable Frequency Divider

采用标准0.18μm CMOS工艺,提出了一种高集成度可编程分频器。该电路所采用技术的新颖之处在于:基于基本分频单元的特殊结构,对除2/除3单元级联式可编程分频器的关键模块进行改进,将普通的CML型锁存器集成为包含与门的锁存器,从而大大提高了电路的集成度,有效地降低了电路功耗,提升了整体电路速度,并使版图更紧凑。仿真结果表明,在1.8 V电压、输入频率Fin=1 GHz的情况下,可实现任意整数且步长为1的分频比,相位噪声为-173.1 dBc/Hz@1 MHz,电路功耗仅为9 mW。

A highly integrated programmable divider is designed according to the standardized 0.18 μm CMOS technology.Based on the special structure of divider 2/3,we improve the key module of the divider,i.e.,changing the ordinary CML D-latch to the latch including AND gate,thus it reduces the power consumption of circuit,improves the overall circuit speed,and makes the layout more compact.Simulation results show that the arbitrary integer frequency ratio is available,the circuit has a phase noise of -173.1 dBc/Hz@1 MHz,and a power consumption of 9 mW in terms of supply voltage of 1.8 V and input frequency of 1 GHz.