基于FPGA的全搜索运动估计硬件电路设计

Design of full search motion estimation hardware circuit based on FPGA

设计了一种分层的二维阵列全搜索运动估计硬件电路。与传统的二维阵列全搜索运动估计电路相比,它在处理单元(PE)的并行结构设计以及存储器设计方面作出了改进,节约了硬件资源和编码时间。根据各模块的时序关系合理安排并行流水线结构,采用一列像素并行处理,实现了运动估计实时编码。

A hierarchical two-dimensional array full search motion estimation（ME） hardware circuit is designed in this paper. Compared with traditional two-dimensional array full search circuit, the improvement of PE parallel structure design and storage design saves hardware resources and coding time. According to the timing relationship of each module, the parallel pipeline structure is reasonable organized. The circuit can deal a column of pixels in one cycle and realizes ME real-time encoding.