快闪存储器阈值电压分布读取电路设计

Threshold voltage distribution readout circuit design for flash memory

提出了一种浮栅型快闪存储器(flash memory)阈值电压分布读取方法。其读出电路结构主要包括电容反馈互导放大器(capacitor feedback trans-impedance amplifier,CTIA)和8b循环型模数转换器(cyclic analog-to-digital converter),以上电路将存储单元的阈值电压进行数字量化输出。此外芯片还集成了译码电路、高压电路、偏置电路和控制电路等辅助电路。上述设计采用0.13μm 2P3M NOR快闪存储器工艺,芯片面积为2.1mm×2.8mm,其中存储阵列包含1 024×1 024个存储单元。测试结果表明该读取电路能够精确地读取快闪存储器的阈值电压分布,可以用来进行存储阵列器件和工艺的离散性等特性研究,也可以用于编程/擦除算法的优化设计。

This paper describes a readout circuit for the flash memory threshold voltage distribution. This circuit includes a capacitor feedback trans-impedanee amplifier （CTIA） and an 8 b cyclic analog-to-digital converter which converts the threshold voltages into digital outputs. The system also has horizontal and vertical decoders, a high voltage generator, a bias module and a timing control circuit. The chip was fabricated using 0. 13 μm NOR flash memory process with 1 024 × 1 024 cells and a 2. 1 mm × 2.8 mm die size. Tests show that this readout circuit accurately depicts the threshold voltage distribution. The circuit can also be used to analysis the discreteness of memory cells and system processes and to improve program/erase algorithms.