摘要
This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.
This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.
基金
supported by the National Science Foundation for Young Scientists of China(No.61306029)
the National High Technology Research and Development Program of China(No.2013AA014103)
