High dV/dt immunity MOS controlled thyristor using a double variable lateral doping technique for capacitor discharge applications

An analysis model of the dV/dt capability for a metal-oxide-semiconductor （MOS） controlled thyristor （MCT） is developed. It is shown that, in addition to the P-well resistance reported previously, the existence of the OFF-FET channel resistance in the MCT may degrade the dV/dt capability. Lower P-well and N-well dosages in the MCT are useful in getting a lower threshold voltage of OFF-FET and then a higher dV/dt immunity. However, both dosages are restricted by the requirements for the blocking property and the forward conduction capability. Thus, a double variable lateral doping （DVLD） technique is proposed to realize a high dV/dt immunity without any sacrifice in other properties. The accuracy of the developed model is verified by comparing the obtained results with those from simulations. In addition, this DVLD MCT features mask-saving compared with the conventional MCT fabrication process. The excellent device performance, coupled with the simple fabrication, makes the proposed DVLP MCT a promising candidate for capacitor discharge applications.