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内建自测试中多输入特征寄存器的硬件开销的减少 被引量:1

Grouping Compression of Output Signals for Reducing the Hardware Overhead of MISR
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摘要 在内建自测试中 ,针对随机向量测试 ,本文提出了一种通过输出信号分组压缩来减少多输入特征寄存器 MISR的硬件开销的方法。该方法是在分析输出信号之间相关性的基础上 ,根据给定的 MISR阶数构造具有最小相关度的输出信号集合组 ,以此来减少输出信号分组压缩时的故障覆盖率损失。 In built-in self-test according to the random test the paper presents a method of grouping compression of output signals for reducing the hardware overhead of MISR.Based on the analysis of relevance weight among output signals the method constructs the set group of output signals with minimum relevance weight to reduce the loss of fault coverage using grouping compression,and the method needs no auxiliary circuity.
出处 《微处理机》 2001年第1期14-18,共5页 Microprocessors
关键词 内建自测试 多输入特征寄存器 门电路 故障覆盖率 硬件开销 Built in self test,MISR,Minimum relevance weight,Fault coverage
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参考文献4

  • 1[1]Jacob Savir. Reducing the MISR Size. IEEE Transactions on Computers, 1996 (8): 930~938
  • 2[2]Krishnendu Chakrabarty and John P Hayes. Test Response Compaction Using Multiplexed Parity Trees. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 1996 (11): 1399~ 1408
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同被引文献7

  • 1Paschalis A, Gizopoulos D. An Effective BIST Architecture for Fast Multiplier Cores[A]. Design, Automation and Test in Europe Conference[C]. Munich: IEEE, Inc, 1999. 117-121.
  • 2Nakamura S. Algorithms for Iterative Array Multiplication[J]. IEEE Trans on Computers, 1986, 35(8) : 713-719.
  • 3Wallace C S. A Suggestion for a Fast Multiplier[J]. IEEE Trans on Elecronic Computers, 1964, 13( 1): 14-17.
  • 4Takach A B, Jha N K. Easily Testable Gate Level and DCVS Multipliers[J]. IEEE Trans on Computer-Aided Design, 1991, 10(7):932-942.
  • 5Hong S J. The Design of a Testable Parallel Multiplier[J]. IEEE Trans on Computers, 1990, 39(3) : 411-416.
  • 6Margala M, Chen Xianling. Design Verification and DFT for an Embedded Reconfigurable Low-power Multiplier in System-on-chip Applciations[A]. 14th Annual IEEE International ASIC/SOC Conference[C]. Arlington: IEEE, Inc, 2001. 230-234.
  • 7蔡晨曦,王秀坛,彭应宁.基于两维压缩特征字分析的BIST性能分析[J].系统工程与电子技术,2001,23(9):1-4. 被引量:1

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