摘要
乘法器是数字信号处理系统中的关键。流水线乘法器可以以较小的代价获得较高的平均速度。本文给出了流水线乘法器的结构;提出了两种改进型Domino加法器电路;对改进型电路作了分析和模拟。模拟结果表明,采用新的改进型Domino电路后,流水线乘法器的速度可以显著提高。
Multiplier is the key in the Digital Signal Processing System. Pipelined Multiplier canachieve high speed with lower cost. In this paper, the structure of pipelined multiplier is given;two new modified Domino adders are proposed;the circuits are analysed and simulatedwith SPICE.The results show that the speed of the pipelined multiplier has been improvedsignificantly when the modified Domino adders are adopted.
