摘要
提出用 CMOS源极跟随缓冲电路以较少的电路段数快速驱动大电容负载 .HSPICE模拟结果表明 ,在负载电容为基本栅电容的 10 0倍及 6 0 0 0倍时 ,CMOS源极跟随缓冲电路具有高于多段倒相器缓冲电路的负载驱动能力 ,且占有面积小 .从而较好地解决了高速驱动芯片内各种数据传输及外部负载的问题 .该电路结构简单 ,易于实现 ,且制作工艺与标准 CMOS工艺完全兼容 .
A novel CMOS source-follower buffer circuit is presented,which has a faster drivability for large capacitance loads than the tapered inverter chains,due to the characteristic of the CMOS source follower.When driving the large capacitance that is 100 times/6000 times as high as the original capacitance by an elemental inverter,two-stage combined source-follower/inverter buffer is 15% faster than the faster tapered inverter-chain buffer of eight-stage,with smaller wafer area.This circuit structure is simple and can be realized by the standard CMOS process easily.
