高信噪比的VFC/DPLL数据采集装置

A VFC/DPLL -in Data Acquisition Device With High S/N Ratio

文中介绍了由VFC芯片鉴频,鉴相器(PFD)组成的数字锁相环路(DPLL)抑制噪声的原理和有关参数的选择和计算;讨论了由DPLL和微处理机结合组成的数据采集系统,信噪比改善的可能性。

This paper discussed the principle of reducting noise using DPLL(Digital Phase -locked loop) composed by VFC chips and PFD (phase - Frequency discriminator), selecting and calculating of relative parameters; Data acquisition system composed by DPLL and mcro-processor the possibility of improving S/N ratio are recommended.