弱对偶基下比特并行RS编码器的设计

Design of Bit Parallel RS Encoder Based on Weak Dual Basis

讨论了高速 RS码编码器的设计问题。研究了有限域元素在弱对偶基 ( WDB)下的表示 ,基于弱对偶基下的最优弱对偶基的计算方法 ,给出了有限域比特并行乘法器的设计过程 ,并且利用这样的乘法器构成了广泛应用的 RS( 2 55,2 2 3)码的编码器。 RS( 2 55,2 2 3)码的编码器的复杂度定量的分析结果表明 :弱对偶基下比特并行乘法器设计复杂度降低 ,便于 VLSI实现。编码器的数据吞吐率可达较高值 。

The high speed design problem of RS encoder is discussed.The presentation of finite field element under weak dual basis is studied. Based on the calculation method over the optimal weak dual basis, the design process for the finite field bit parallel multiplier is given and Reed Solomon (RS)(255, 233) encoder is constructed by use of this multiplier. The quantitative analysis results for RS (255, 233) encoder complexity have shown that the reduction of the design complexity for the bit parallel multiplier under weak dual basis is convenient for the implementation of VLSI. The data throughput of the encoder can be a higher value and is good for the highs speed applications.