抑制冗余优先编码器的逻辑设计

Logic design of priority encoder by restraining redundancy

基于低功耗设计的要求 ,对传统设计的优先编码器中的冗余现象加以研究 ,利用冗余抑制技术重构基于门级设计优先编码器电路结构 .该优先编码器经 PSPICE模拟验证具有正确的逻辑功能 。

According to the design requirement of low power dissipation, this paper makes an inspection of the redundancy correlated with priority encoder and reconstructs the circuits at the gate level by using the technique of restraining redundancy. PSPICE simulation shows that the new structure of the priority encoder has the correct logic function and can reduce the power dissipation.