FFT处理器的高密度可编逻辑器件实现

Complex Programmable Logic Devices Implementation of FFT Processor

为了提高快速离散傅立叶变换 (FFT)的处理速度 ,研究了一种宜于高密度可编逻辑器件(CLPD)实现FFT处理器的硬件结构 ,并利用CPLDFLEX10K设计和实现了 12 8点FFT单片处理器。系统的仿真结果表明 ,该处理器运算结果正确 ,在系统时钟频率为 2 0MHz时 ,12 8点复数FFT处理器的计算时间小于 2 30 μs。研究表明 :CPLD与FFT的结合将提高FFT的处理速度 。

In order to accelerate the working speed of a FFT processor, this paper presents a hardware structure of a FFT processor, which is suitable for CPLD , and the 128-point FFT single-chip processor is realized by means of FLEX10K CPLD and MAX+PLUS II software. The calculation time of the processor is less than 230uS. The research proves that the combination of CPLD and FFT increases the working speed of FFT processors and raise the level of application .