集成电路设计中的逻辑加速优化算法

Logic Speed-up Optimization in IC Design

为了尽可能提高实际电路的运行速度, 针对传统"逻辑优化"过程中的问题和不足, 以"多级逻辑变换"技术为核心，提出了"逻辑加速优化"设计方法。在优化过程中,既考虑了与工艺无关的优化,也考虑了工艺库单元的实际延时性能;并且,由于对原电路进行了较大规模的重建,因此可得到传统"分解"技术无法生成的逻辑结构。

In order to optimize the circuit's delay, we present a new method named 'logic speed-up optimization' which aims at the drawback of the conventional logic optimization. The key step of the method is 'multilevel logic transformation', and it has two virtues: first, it considers both of the technology independent optimization and the cell library's capability; second, it reconstructs the circuit's structure so that the circuit can get some new logic structures which can not be obtained by conventional logic decomposition.