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集成电路测试机发展简史 被引量:1

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摘要 本文介绍了集成电路测试机(IC TESTER)的发展简史,包括第一台测试机到目前的第三代测试机的主要特点,可以看出集成电路测试机的发展方向。
出处 《集成电路应用》 2001年第3期18-18,46,共2页 Application of IC
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  • 1肖明清,朱小平,夏锐.并行测试技术综述[J].空军工程大学学报(自然科学版),2005,6(3):22-25. 被引量:56
  • 2王琛.ATE测试成本优化[J].电子工程师,2006,32(11):14-16. 被引量:3
  • 3Eric Liau, Doris Schmitt-Landsiedel. A novel semiconductor test equipment concept: Automatic test equipment with computational intelligence technique ( ATE-CIT ) [C]. In Proceedings of Instrumentation and Measurement Technology Conference Como, Italy, 18-20 May, 2004, pp. 2144-2149.
  • 4Volkerink E.H, Khoche A, Rivoir, J, Hilliges K. D.Test economics for multi-site test with modern cost reduction techniques [C]. In Proceedings of 20th IEEE VLSI Test Symposium, 2002, pp. 411-416.
  • 5Gosling W. Twenty years of ATE[C]. In Proceedings of International Test Conference, 1989, pp. 3-6.
  • 6Waivio N. Parallel test description and analysis of parallel test system speedup through Amdahl's law [C]. In Proceedings of 2007 IEEE Autotestcon, pp. 735-740.
  • 7Amdahl G. M. Validity of the single processor approach to achieving large scale computing capabilities [C], In Proc. of AFIPS Spring Joint Computer Conf. 30, Atlantic City, NJ 30, April 1967, pp. 483-485.
  • 8Moncrieff D, Overill R.E, Wilson S. Heterogeneous computing machines and Amdahl' s law [J]. Parallel Computing, 1996, 22 ( 3 ) : 407-413.
  • 9Velamati N, Daasch R. Analytical model for multi-site efficiency with parallel to serial test times, yield and clustering [C]. 2009 27th IEEE VLSI Test Symposium, pp. 270-275.
  • 10Volkerink E. H, Khoche A, Rivoir J, Hilliges K. D.Test economics for multi-site test with modern cost reduction techniques [C]. In Proceedings of 20th IEEE VLSI Test Symposium, 2002, pp. 411-416.

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