基于位串行分布式算法和FPGA实现FIR电路的研究

Bit-serial Distributed Arithmetic for Implementation of FIR Filters Using FPGAs

本文提出了一种采用现场可编程门阵列器件FPGA实现FIR数字滤波器硬件电路的方案 ,该方案基于只读存储器ROM查找表的位串行分布式算法。并以一个十六阶低通FIR数字滤波器电路的实现为例说明了设计过程 ,所设计电路通过了软件验证和硬件仿真 ,结果表明电路工作正确可靠 ,满足设计要求。

In this paper, a method to implement the FIR digital filters using FPGA is proposed. The bit-serial distributed arithmetic based on the ROM look-up table is employed. A sixteen-tapped low pass FIR filter is taken as an example. The implemented circuit is simulated and the results show that the circuit works reliably and perfectly.