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CeO_2高K栅介质薄膜的制备工艺及其电学性质 被引量:4

Epitaxial Growth of CeO_2 films on Si(100) Substrate and Its Electrical Properties
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摘要 研究了 Ce O2 作为高 K (高介电常数 )栅介质薄膜的制备工艺 ,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用 N离子轰击氮化 Si衬底表面工艺对 Ce O2 薄膜的生长及其与 Si界面结构特征的影响 ,利用脉冲激光淀积方法在 Si(10 0 )衬底生长了具有 (10 0 )和 (111)取向的 Ce O2 外延薄膜 ;研究了 N离子轰击氮化 Si衬底表面处理工艺对 Pt/ Ce O2 / Si结构电学性质的影响 .研究结果显示 ,利用 N离子轰击氮化 Si表面 /界面工艺不仅影响 Ce O2 薄膜的生长结构 ,还可以改善 Ce O2 与 The deposition process of CeO 2,a high K gate dielectric thin film by using the pulsed laser deposition method has been investigated.The epitaxial CeO 2 thin films with (100) and (111) orientations on Si(100) substrates have been grown.The influence of different deposition conditions,including the nitrogen plasma bombardment to Si substrate surface is discussed.The structural and electrical properties of CeO 2 thin films are investigated,as well as interface with Si substrate.It shows that the nitrogen ion bombardment to Si substrate surface can not only change the growth structure but also improve the interfacial electrical properties of CeO 2/Si.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2001年第7期865-870,共6页 半导体学报(英文版)
基金 国家重点基础研究专项经费资助项目 (合同号 :G2 0 0 0 0 3 65)
关键词 高K栅介质 半导体薄膜 氧化铯薄膜 电学性质 制备工艺 high K gate dielectric CeO _2 film nitrided Si surface/interface
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