微处理器中中断电路的高层设计

Interrupt Module Architecture in MCU

文章介绍了一种采用中断执行周期复用、寄存器模型设计中断标识信号的中断电路实现方法，并给出了关键控制信号的 Verilog HDL程序实现。该实现方法可以作为一个功能部件直接在微处理器设计中加以运用；中断标识信号的优先级与触发时刻的考虑对更复杂中断电路的设计也具有很好的借鉴意义。

This paper introduces the method of execution－ cycle multiplexing and the designs of interrupt flag signals using register model in interrupt module architecture. Some control signals are illustrated with Verilog HDL design in detail. Interrupt module presented in this paper can be used directly in MCU designs. The consideration of priority and triggering time are helpful for other complex interrupt module architecture.