冗余抑制的硬件实现及作用过程分析

Hardware mechanism for redundancy restraint and the analysis of their working procedure.

基于低功耗设计的要求 ,本文对数字系统中冗余现象的普遍性进行分析 ,研究了实施冗余抑制功能的各种基本结构 ,并进行了抑制作用的时间分析 ,这些均为在电路的低功耗设计中有效地应用冗余抑制技术提供了研究基础 .

According to the requirements of low power design, this paper makes an inspection of the common redundancy correlated with digital systems, studies various basic structures to implement restraint actions and carries out the time analysis for them. All of the above will provide basic elements to effectively achieve low power designed circuits by applying the technique of redundancy restraint.