逻辑综合中关键门的寻找

Searching for Critical Gates in Logic Synthesis

关键路径一直是电路性能优化的核心问题之一 .门的尺寸调整和插入缓冲器是时间优化的重要方法 .实际上 ,电路拓扑图中最长的路径不一定就是关键路径 ,只有在一定输入下能敏化的最长路径才是关键路径 .因此 ,仅仅按拓扑信息优化最长的路径不一定能真正提高电路的性能 .此外 ,仅仅利用 D-算法判断路径敏化有不足之处 .本文利用电路拓扑找出超出时间限制的路径 ,然后利用改进的 FAN算法—— T- FAN算法 ,提取关键门——即和电路整体延时有关系的门 ,为优化指出具体、准确的目标 .实验表明 ,改进的算法在保证优化效果的前提下 ,能平均减少 30 %～ 40 %优化对象 .

In logic synthesis, critical path is the key problem to improve circuits' performance. Gate-resizing and buffer-inserting are two important methods in timing optimization. A topologically longest path, which can't be sensitized, is not a critical path and is not much useful in timing optimization. In this paper, paths whose delay in topological manner goes beyond timing constraint are picked out, and then according to sensitization standard, critical gates from these paths are extracted by a modified FAN algorithm (T-FAN algorithm). So, timing optimization has accurate targets. The result shows that after optimization false targets are eliminated, which account for 30%-40% of all the target gates.