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浮点加法器中进位传递问题的合并处理 被引量:2

The Combined Design of the Three Carry Propagation in the Floating-Point Adder
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摘要 文章首先介绍了浮点加法器中可能存在的三个进位传递问题,然后论述了这三个进位传递问题合并实现的可行性,最后给出了一种合并设计的方法,并应用于LS RISC微处理器芯片中,缩短了运算路径及芯片的面积,提高了芯片的性能。 In this paper, we first introduce the three carry propagation in the floating point adder, then discuss the feasibility to combine these three to one. At last, we present a scheme of how to combine these carry propagation and implement it in LS RISC Microprocessor. It is obvious that it can shorten the critical path of FALU, minish the area of the chip, and increase the chip's performance.
出处 《微电子学与计算机》 CSCD 北大核心 2001年第3期33-36,共4页 Microelectronics & Computer
关键词 浮点加法器 微处理器 芯片 合并处理 进位传递 Floating-point adder, Microprocessor, Chip, Critical path, Combination
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参考文献3

  • 1[1]IEEE Std 754-1985, IEEE Standard for Binary Floating - point Arithmetic, IEEE, 1985.
  • 2[2]W C Park, S W Lee, O Y Kown, T DHan, S D Kim. Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel, IEICE Trans. Information and Systems e79- d,1996(4): 297 ~ 305.
  • 3[3]Nhon T Quach and Michael J Flynn, An Improved Algorithm for High - speed Floating-point Addiyion. Technical Report: CSL - TR - 90 - 442,1990.

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