摘要
文章描述了基于电流模压控振荡器的锁相环的设计和仿真。锁相环的所有部件都设计在同一芯片上。电路设计基于 1 .2 μm CMOS工艺。HSPICE仿真结果显示 ,锁相环在 5 V外加电源电压时 ,工作在 1 6 MHz到 3 5 0 MHz宽的频率范围内 ,峰 -峰相位抖动小于 1 2 .5 ps,功耗为 2 0m W,锁相环的锁定时间小于 6 0 0 ns。
A phase locked loop (PLL) based on current mode voltage controlled oscillator (VCO) is described. All of the components of the PLL were integrated on one chip. The circuit design is realized in 1.2 μm CMOS technology. HSPICE simulation shows that the PLL operates within the frequency range between 16 MHz to 350 MHz, and the peak peak jitter is less than 12.5 ps. The lock time of the PLL is less than 600 ns.
出处
《微电子学》
CAS
CSCD
北大核心
2001年第5期379-382,共4页
Microelectronics
