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一个128×128 CMOS快照模式焦平面读出电路设计 被引量:2

A 128×128 CMOS Snapshot Readout Circuit Design for Focal Plane Array
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摘要 本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构———DCA(Direct injectionChargeAmpli fier)结构 .该结构像素电路仅用 4个MOS管 ,采用特殊的版图设计并用PMOS管做复位管 ,既可保证像素内存储电容足够大 ,又可避免复位电压的阈值损失 ,从而提高了读出电路的电荷处理能力 .由于像素电路非常简单 ,且该结构能有效消除列线寄生电容Cbus的影响 ,因此该结构非常适用于小像素、大规模的焦平面读出电路 .采用DCA结构和 1 2 μm双硅双铝 (DPDM Double PolyDouble Metal)标准CMOS工艺设计了一个 12 8× 12 8规模焦平面读出电路试验芯片 ,其像素尺寸为 5 0× 5 0 μm2 ,电荷处理能力达 11 2pC .本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序 ,并给出了精确的HSPICE仿真结果和试验芯片测试结果 . A novel CMOS snapshot readout structure called DCA (Direct-injection Charge Amplifier) for focal-plane array (FPA) is presented in this paper.The pixel circuit includes only four MOS transistors.Using PMOSFET as the reset transistor with careful layout design,this pixel circuit not only can keep the in-pixel-capacitance large enough,but also can avoid the threshold voltage loss during the reset for the integration node.Thereby,charge capacity of the readout circuit is increased.Since the pixel circuit is very simple and this structure can eliminate the influence of column bus parasitic capacitance,it is very suitable for large-format small-pixel readout circuit.An experimental 128×128 DCA chip has been designed with 1.2-μm DPDM n-well CMOS technology.The charge handling capacity is 11.2pC with pixel size 50×50μm 2.A description of the readout circuit structure,pixel circuit,detector model,operation principle and chip layout is given in detail.Both excellent simulation results and experimental results of the fabricated DCA readout chip are presented.
出处 《电子学报》 EI CAS CSCD 北大核心 2001年第11期1454-1457,共4页 Acta Electronica Sinica
关键词 快照模式 焦平面 读出电路 电子成像系统 CMOS电路 focal plane array readout circuit direct injection snapshot DCA structure
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参考文献1

  • 1Ma Shyhyih,IEEE 1998 Custom Integration Circuit Conference,1999年,287页

同被引文献7

  • 1汪剑平.红外焦平面阵列的读出电路结构[J].传感器世界,2005,11(9):29-32. 被引量:2
  • 2Jan Crols, Michel Steyaert. Switched-opamp.. an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages [ J ]. IEEE Journal of Solid-State Circuits, 1994,29 (8) :936 - 942.
  • 3Willy M. C Sansen. Analog Design Essentials [ M ]. Netherlands : Springer, 2006.648 - 651.
  • 4G Bonfini, et al. An ultra-low power switched opampbased 10-b integrated ADC for implantable biomedical applications [ J ]. IEEE Transanctions on Circuits and Systems ,2004,51 ( 1 ) : 174 - 177.
  • 5R Cannata. Design and analysis of IR focal plane electronics [ J ]. SPIE Short Course Notes, Orlando, April 1997.
  • 6J L Vampola. Readout electronics for infrared sensors [J]. The Infrared and Electro-Optical Systems Hand- book, Vol. 3, Chapter 5, SPIE Optical Engineering Press, 1993,286 - 324.
  • 7S G Chamberlain. Photosensity and scanning of silicon image detector arrays [ J ]. IEEE Journal of Solid-State Circuit, June 1969, SC - 4 : 333 - 342.

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