摘要
本文详述了同步开关噪声 (SSN)影响VLSI电路可靠性的一个主要因素 :芯片 封装界面的寄生电感 .根据在芯片中插入电源 /地线引脚 ,减小芯片 封装界面的寄生电感的思想 ,提出一种简便有效的基于SSN性能的输出驱动器优化布局方法并将之集成到VLSI设计流程中 .用 0 6微米CMOS工艺进行了验证 .结果表明 :该优化设计可有效降低SSN对VLSI电路可靠性的影响 .
The effects of Simultaneous Switching Noise (SSN) on VLSI are elaborated. And an automatic CAD tool to optimize SSN performance of VLSI is developed with optimized placement of inserting ground pads. Under the conditions provided, the equations in this procedure can be used in a very high-speed environment. A set of test chips taped out by using this CAD tool proved that the procedure can effectively reduce the SSN, which is more serious when feature size of VLSI is scaled down.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2001年第11期1471-1474,共4页
Acta Electronica Sinica
基金
上海应用材料研究与发展基金 (No.0 0 0 2 1 1 998)
