多缓存共享的ATM交换机体系结构及其性能

Multibuffer Shared ATM Switch Architecture and Its Performance Analysis under Uniform Traffic

提出了一种新的ATM交换机体系结构 ,输出模块中的多个缓存实行共享 .这既充分利用了共享缓存和输出缓存的优点 ,又克服了共享缓存的带宽限制 .性能分析表明 ,在均匀业务流的情况下 ,当负载为 0 .9时 ,为使ATM交换机的信元丢失率小于 1 0 -9,每个缓存所需的容量仅为 1 6个信元长度 .

This paper presents a novel ATM switching architecture where many buffers placed in an output module are partially shared, which takes advantages of output buffer and shared buffer. And these shared buffers bring an advantage that the speed of accessing each of these buffers do not need to be very high and these buffers can write/read many cells in a parallel way. The performance of this ATM switching system is analyzed under a uniform traffic. And the results show that the cell loss probability of this ATM switching system is less than 10 -9 and the capacity for each shared buffer is 16 cell length.