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星用大容量静态存储器多位翻转实验研究 被引量:2

Experimental Investigation of Heavy Ions Induced SEMU in High-Density SRAMs
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摘要 给出典型大容量静态存储器(SRAM)的多位翻转实验研究 结果。用HI-13串列型静电加速器和兰州重离子加速器(HIRFL)加速的重离子轰击样品,用 一套基于 网络协议的高分辨率SRAM单粒子效应检测系统检测发生的多位翻转。实验结果表明多位翻转 可以由多种机制产生:在两种Hitachi SRAM中检测到的同一字节多位翻转(SMU)是由单个离 子产生的电荷被相邻敏感节点共享所致;当IDT71256中写入测试图形“00”时,其外围电路 中产生的单粒子瞬时脉冲(SET)引起多达8位的SMU;离子大角度掠射下,IDT71256中检测到 了同一事件多位翻转(SEMU)。同时预示了两种Hitachi大容量SRAM在地球同步轨道和两条太 阳同步轨道发生SMU的频度。 Single event multiple upset (SEMU) experimental results of high-density static random access memory (SRAM) are presented.The devices un der tests (DUTs) were bombarded by heavy ions from HI-13 tandem accelerator an d h eavy ion research facility in Lanzhou (HIRFL).A high-resolution tester for sing le event upset (SEU) in SRAMs,which is based on network communication protocol, was utilized to detect SEMUs occurred.Experimental results show that different me chanics can cause SEMU,SMU in HM628128ALP and HM628512LP were due to diffusing o f changes created by single ion to neghbouring junction.It was confirmed that sin gle event transients (SET) occured in peri-pheral circuit could cause SMU a nd pro ducts of spallation reactions of incident heavy ions with encapsulation material s also could contribute to SEMUs in case of glancing incidence.SMU rates of Hita chi SRAMs in geosychronous orbit and two sunsychronous obits were predicted. Subject Term Static storage Radiation effect Multiple bit u pset Experimentation
出处 《中国空间科学技术》 EI CSCD 北大核心 2001年第5期40-46,共7页 Chinese Space Science and Technology
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参考文献4

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同被引文献22

  • 1Qingxiang Zhang,Mingdong Hou,Jie Liu,Honglou Zhen.σ-LET curve obtained with heavy ions accelerated by HIRFL[J].Chinese Science Bulletin,2002,47(17):1431-1433. 被引量:2
  • 2Baumann, R. Soft errors in advanced computer systems [ J ]. IEEE Design & Test of Computer,2005,22(3) :258-266.
  • 3Tipton A D, Pellish J A, Reed R A, et al. Multiple-bit upset in 130nm CMOS technology [ J. IEEE Transaction on Nuclear Science,2006,53(6) :3259-3264.
  • 4Swift G M, Guertin S M. In-flight observation of multiple- bit in DRAMs [ J ]. IEEE Transactions on Nuclear Sci-enee,2001,47(6):2386-2391.
  • 5Shirvani P P, Sexena N R, McCluskey E J. Software-im- plemented EDAC protection against SEUs [ J ]. IEEE Transactions on Reliability,2000,49(3) :273-284.
  • 6E1-Medany W M, Harrison C G, Farrel P G, et al. VHDL implementation of a BCH minimum weight decoder for double error [ C 1 JJ Proc of the 18th Radio Science Conf.. 2001:361-368.
  • 7Argyrides C, Zarandi H R, Pradhan D K. Multiple up- sets tolerance in SRAM memory [ C ]// IEEE Internation- al Symposium on Circuits and Systems. 2007:365-368.
  • 8Bossert M, Bezzateev S. Decoding of interleaved RS codes with the Euclidean algorithm [ C ] JJ IEEE International Symposium on Information Theory. 2008:1803-1807.
  • 9Nasser R, Draper J. DEC ECC design to improve memory reliability in sub-100nm technologies [ C ] JJ IEEE Inter- national Conference on Electronics, Circuits and Systems. 2008:586-589.
  • 10Nasser R, Draper J. Parallel double error correction code design to mitigate multi-bit upsets in SRAMs [ C ]//34th European ESSCIRC. 2008 : 222-225.

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