基于扫描的低测试功耗结构设计

DESIGN OF SCAN-BASED LOW TESTING POWER ARCHITECTURE

在集成电路设计中 ,面积、功耗和可测性是 3个最为重要的优化指标 .测试成本正随着集成电路规模的不断增大而提高 ,因此在设计中加入可测性设计的考虑已成为共识 .基于扫描的可测性设计方法是目前应用最广泛的方法之一 .加入扫描结构可以大大提高电路系统的测试性能 ,但同时也会给系统的面积、性能、功耗等带来一些负面影响 .提出了一种考虑低功耗因素的可测性设计方法 .计算数据显示 ,与传统扫描设计方法相比 ,这种方法在改善系统测试功耗方面具有突出的优势 .

Area, power and testability are three important facts in the optimization of VLSI circuits. The cost of test is increasing because the scale of integrated circuits is getting higher and higher. Scan-based techniques of design for testability are widely implemented in VLSI circuits to improve their testability, although trade off is needed for area, performance and power. A novel scan-based technique taking into account the testing power is presented in this paper. Measured result shows it has the advantage of testing power reduction, while the cost of area and testing time are limited.