Verilog语言形式化语义研究

Study on the Formal Semantics of Verilog

在连续离散混合时间模型中考虑 Verilog的语义行为 ,将混合模型中的一个区间作为 Verilog程序一次运行过程的指称 .提出了一种扩展的 ITL来描述这种混合区间 ,从而给出 Verilog的形式语义 .这种语义定义不仅考虑到了各种语言成分的最终执行结果 。

The semantics of Verilog program are studied in a discrete-continuous hybrid time model. A hybrid interval is denoted as the description of a run of Verilog program. An extended ITL is presented to describe this kind of hybrid interval. This semantics not only considers the ultimate execution effects of all kinds ingredients of language, but also gives their temporal characteristics.