基于IBIS模型的CMOS电路同步开关噪声的计算和优化

Computation and Optimization of Simultaneous Switch Noise in CMOS Circuits Based on IBIS Model

基于高速数字 I/O缓冲器瞬态行为模型计算并优化了 CMOS集成电路的同步开关噪声(SSN) .简述了用 IBIS(I/O Buffer Information Specification)数据文件构造高速数字 I/O缓冲器的瞬态行为模型的推导过程 ,利用序列二次规划法 (SQP)对 CMOS电路的寄生参数和传输线的主要物理参数进行了优化分析 ,减小了 CMOS电路的 SSN.

Based on the transient behavioral models of high-speed digital I/O buffers, the simultaneous switching noise (SSN) in CMOS circuits was analyzed and optimized. A simple derivation procedure of building transient behavioral models of high-speed digital I/O buffers from the latest version IBIS modeling data was given. With successive quadric processing method, the parasitic parameters and the main physical parameters of transmission line in CMOS circuits were optimized to reduce the simultaneous switching noise.