高速芯片封装结构的同步开关噪声分析及抑制

Analysis and Suppression of Simultaneous Switching Noise in High-Speed Chip Package

基于 BIS模型 ,提出了一种新颖、简单地估算高速芯片封装结构同步开关噪声 (SSN)的方法 .通过与电路模拟方法的比较 ,表明了该方法的有效性 .基于对多种抑制封装结构 SSN措施的分析与讨论 ,给出了低 SSN的高速封装结构设计原则 .

Based on the IBIS model, a simple method was proposed to estimate the simultaneous switching noise (SSN) of the high-speed chip package. Compared with the results of circuit simulation, it demonstrated that this method is effective. Relied on the analysis and discussions of many measures for suppressing the SSN of the package, some design guidelines for the high-speed chip package with low SSN were presented.