基于.25um工艺的层次式时间驱动的版图设计

Hierarchical Timing-driven Layout based on .25um Technology

集成电路(IC)发展到了系统芯片(SOC)时代。超深亚微米系统芯片具有规模大、复杂度高、系统时钟频率快的特点,传统的设计流程由于设计规模有限和时序难以收敛等原因,已难以适用于系统芯片的设计;常用的展平式(flat)版图设计方法,会导致工具处理能力严重不足。本文提出了一个完整的系统芯片的设计流程以及基于该流程的层次式、时间驱动的版图设计方法。设计过程采用自上而下的(top-down)的约束分配和时间驱动方式以满足时延约束,实现时序收敛;布局规划采用层次式模块分割以适应芯片规模大的要求。针对8VSB芯片采用.25um工艺在商用软件平台上对上述新方法进行了验证。实验结果表明,60万门的8VSB芯片速度可达到108Mhz。

Integrated circuit design has been developed into the VDSM-based SOC era. SOC means the whole system can be integrated into one chip. However, SOC design with VDSM technology encounters difficulties arising from large scale, complexity and high clock frequency. These problems cannot be overcome by traditional design process because of its design-scale limitation and slow convergence of timing. Traditional flatten layout method are not robust enough to deal with large quantity of data coming out from design process. Therefore, a complete SOC design process with associated hierarchical & timing-driven layout method is proposed, in which top-down constraint budget and timing-driven strategy are used to obtain timing convergence, while hierarchical module partitioning can cope with the large scale of SOC. The result of 600k 8VSB chip design experiment with 0.25um technology provided a speed of 108Mhz.