利用FPGA和DSP结合实现雷达多目标实时检测

Radar Multi-Target Real-Time Detection with FPGA and DSP

在高速并行流水信号处理中 ,ASIC(FPGA) +DSP +RAM是目前国际流行的一种方式 ,尤其是FPGA +DSP +RAM更适合中国的国情 .本文利用FPGA的算术逻辑单元与外部存储器相结合 ,解决了线路板面积有限与雷达数据处理需要大量存储空间的矛盾 ;利用FPGA的并行流水特点解决了雷达数据的实时处理与有限的DSP处理速度之间的矛盾 ;而FPGA处理结果的航迹相关、FPGA运行模式的控制和与上位机之间的通信与数据交换等工作利用DSP完成 ,从而达到系统的最佳配置 .目前系统已通过验收 。

ASIC (FPGA)+DSP+RAM is popular model in high speed parallel pipeline signal processing. It is especially suitable for China. Based on the combination of FPGA's configurable logic blocks and external memory, the problem exist between limited PCB size and huge memory space is solved in radar data processing. On the other hand, the parallel pipeline functions of FPGA resolve the problem between mass radar data real-time processing and limited DSP speeds. The track correlation after using FPGA, FPGA's operation model control, data communication and exchange between DSP and host computer are all done by DSP. Therefore the optimal system structure is established. The system is checked and accepted, and satisfies the requirement of the design.