摘要
研究一种跳频通信机低杂散、低相噪快速捷变频率合成器的实现途径 .该合成器采用 DDS芯片 (AD985 2 )激励 PLL(Q32 36 )的方案 ,控制单元采用 TI公司的 DSP芯片TMS32 0 C31,将 DDS极高的频率分辨力与锁相式频率合成器较高的工作频率结合起来 ,获得了更高的频率合成性能 .其主要技术指标为 :相位噪声小于 - 10 0 d B/ Hz(偏离载频1k Hz处 ) ,杂散电平小于 - 6 0 d B.
An approach of a low spurious, low phase noise, agile frequency synthesizer was presented. The synthesizer adopted DDS chip (AD9852) as the excitation for the PLL chip (Q3236) and TMS320C31 of TI as its control unit. By combining the lutra high frequency resolution of DDS and the high operation frequency of PLL, better performance can be achieved. The phase noise of the synthesizer output is less than -100 dB/Hz(away from carrier 1 kHz) and the spurious level is less than -60 dB.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2001年第6期753-756,共4页
Transactions of Beijing Institute of Technology
基金
部级预研项目
