8位RISCMCU Core设计

Design of 8 bit RISC MCU Core

本文介绍基于RISC体系结构的微控制器IP核 --RISCMCUCore的设计与实现。主要包括指令集分析、指令译码与控制器的设计。RISCMCUCore规则的指令格式缩减了译码单元规模 ;优化设计的时序控制逻辑 ,使取指部件与执行部件同时工作 ,实现了二级流水线 ,达到单周期单指令(程序转移指令例外 )的执行速度。RISCMCUCore用可综合的VerilogHDL描述 ,按设计流程进行各级仿真验证 ,最后在VerilogXL上完成系统级指令测试。

This paper introduces a Microcontroller IP Core -- RISCMCU Core design and realizes. The IP Core is base on RISC structure. The text detail instructions analyze, instructions decipher and design of controller. Regular instruction format make way realize and reduce circuit; Special time sequence that design control logic, realize 2-stage pipeline. This Core executes one instruction in single period (Except instructions of program jumping). RISCMCU Core divide into module describe with Verilog HDL that can be synthesized, Carry on behavior grades of overall verify, RTL emulation. And Test in system level by Verilog XL of Cadence.