多分辨率重采样压缩算法硬件系统体系结构研究

Study on Hardware Compression System Architecture for RBC Algorithm

主要介绍基于多分辨率重采样算法的图像实时压缩系统体系结构设计。文章首先简要描述多分辨率重采样图像压缩算法 ,然后探讨以硬件系统实现该算法所可能采取的多种不同体系结构。在分析比较各种体系结构特点基础上 ,重点阐述以大规模专用集成电路作为系统核心的体系结构 ;为完成多分辨率重采样图像压缩专用集成电路设计 ,对压缩算法进行了并行化、模块化、层次化处理 ,提出实现多分辨率重采样图像压缩算法的超大规模集成电路结构 ,并且以可编程序门阵列实现。实验结果表明 ,以该结构实现的硬件压缩系统 ,在保证恢复图像质量前提下 ,体积小、质量轻、功耗低、数据处理速度快 ,在原理上 。

VL SI architecture based on the RBC algorithm is developed. The architecture is fastwith low hardware complexity,which can compute huge amount of data at very high speed for real- time compression application and match the requirement of VL SI architecture,regularity,modularity,locality.Based on the architecture,special chip for real- time image compression is designed and manufactured with Field Programmable Gate Array.The peak processing speed of the ASIC can reach2 88Mbit/s and their power consumption is lower than1W.