数字电路可测性设计的一种故障定位方法

A Fault Location Approach for the Testable Realization of Logic Functions

在逻辑函数Reed Muller模式的电路可测性设计方面 ,文章采用AND门阵列和XOR门树结构来设计电路 ,提出了一种设计方案 ,可实现任意逻辑函数的功能 ,而且所得电路具有通用测试集和完全可故障定位的特点。给出了进行故障定位的方法 ,并可把它应用于其他相关电路的可测性设计。

An approach of design for testability(DFT) for logic functions is presented in the paper, which employs AND gates and XOR gates tree to realize the generalized Reed Muller expression of arbitrary logic functions. The major features of the approach are: 1) The circuits adopting the DFT techniques in the paper are totally fault locatable. 2) The circuits have universal test sets for fault detection, the cardinality of the test sets is ( n+5 ), where n is equal to the number of input variables in the logic function. A fault location method for the circuits is presented, which can identify all fault equivalence classes in the AND gates, and the faults in XOR gate tree in the circuits. [