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系统级体系结构仿真器的研究与实现 被引量：1

Reserch and Implementation of System Level Architectural Simulator
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摘要 系统级体系结构仿真器是可以作为一个虚拟目标机器运行的软件系统 ,它可以实现对单 (多 )处理器、内存系统、Cache和外部设备等子系统的功能模拟 .在体系结构设计和操作系统开发等工程中 ,体系结构仿真器有着广泛的应用 .本文介绍了一个基于 MISC CPU和 SPARC体系结构的系统级仿真器 A system level simulator is a software system that works as a virtual target machine by simulating the function of uniprocessor/multiprocessor,memory system,cache,devices,etc,which is playing an increasingly important role in the design of architecture and the development of operating system.A MISC CPU and SPARC architecture based system level simulator named FMCS is introduced in this article.
作者 陆岚 王克祥 熊悦 赵振西
机构地区 中国科学技术大学计算机科学技术系
出处 《小型微型计算机系统》 CSCD 北大核心 2002年第1期14-17,共4页 Journal of Chinese Computer Systems
关键词 仿真器 系统级体系结构仿真器 设计 FMCS system level simulator architecture instruction set
分类号 TP337 [自动化与计算机技术—计算机系统结构]
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同被引文献10

  • 1S S Mukherjee,Joel Emer,S K Reinhardt.The soft error problem:An architectural perspective[C].In:Proc of the 11th Int'l Symp on High-Performance Computer Architecture.Los Alamitos,CA:IEEE Computer Society Press,2005.243-247
  • 2Robert Baumann.Soft errors in commercial semiconductor technology:Overview and scaling trends[C].In:IEEE 2002 Reliability Physics Tutorial Notes,Reliability Fundamentals.Piscataway,NJ:IEEE Press,2002
  • 3S S Mukherjee,et al.A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor[C].In:Proc of the 36th Int'l Symp on Microarchitecture.Los Alamitos,CA:IEEE Computer Society Press,2003
  • 4N Wang,T Rafacz,J Quek,et al.Characterizing the effects of transient faults on a modern high-performance processor pipeline[C].In:Proc of the Int'l Conf on Dependable Systems and Networks.Los Alamitos,CA:IEEE Computer Society Press,2004
  • 5S Kim,A K Somani.Soft error sensitivity characterization for microprocessor dependability enhancement strategy[C].In:Proc of the Int'l Conf on Dependable Systems and Networks.Los Alamitos,CA:IEEE Computer Society Press,2002.416-425
  • 6P Shivakumar,et al.Modeling the effect of technology trends on the soft error rate of combinational logic[C].In:Proc of the Int'l Conf on Dependable Systems and Networks.Los Alamitos,CA:IEEE Computer Society Press,2002
  • 7G P Saggese,et al.An experimental study of soft error in microprocessors[J].IEEE Micro,2005,25(6):30-39
  • 8Joel B Nickel,Arun K Somani.REESE:A method of soft error detection in microprocessors[C].In:Proc of the Int'l Conf on Dependable Systems and Networks.Los Alamitos,CA:IEEE Computer Society Press,2001.401-410
  • 9Nicholas J Wang,Sanjay J Patel.ReStore:Symptom based soft error detection in microprocessors[C].In:Proc of the Int'l Conf on Dependable Systems and Networks.Los Alamitos,CA:IEEE Computer Society Press,2005
  • 10M R Guthaus,J S Ringenberg,D Ernst,et al.Mibench:A free,commercially representative embedded benchmark suite[C].In:IEEE 4th Annual Workshop on Workload Characterization.Los Alamitos,CA:IEEE Computer Society Press,2000.266-277

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小型微型计算机系统
2002年 第1期

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