用复杂可编程逻辑器件(CPLD)实现的数字钟控系统

Realization of Digital Clock Control System by Complex Programmable Logic Device (CPLD)

以Lattice半导体公司的ispLSI10 3 2E - 70PLCC84为典型器件 ,ISPSynarioSystem3 .0为编程软件 ,介绍了利用在系统高密度可编程逻辑器件构成数字钟控系统的基本方法。

A basic method for constructing the control system of digital clock using CPLD,ispLS1032-70PLC84(Lattice Semiconductor Corporation)and ISP Synario System3.0 Software is introduced.