基于刻蚀工艺的IC关键面积计算模型与实现方法

Computation Model and Realization Method of IC Critical Area Based on Etching Process

在 IC的制造过程中 ,由于工艺的随机扰动 ,过刻蚀和欠刻蚀造成了导线条的宽度和线间距的变化 .论文在分析过刻蚀和欠刻蚀对 IC版图影响的基础上 ,提出了基于工艺偏差影响的 IC关键面积计算新模型和实现方法 .

Over etching or under etching in IC process causes the variation of the linewidth and spacing between two parallel lines because of the random disturbance of the process.The influence on over etching and under etching to IC layout is analyzed,the computation model and realization method of IC critical area are presented.The simulation result is in agreement with the theoretical analysis.