摘要
主要介绍了CPLD设计单稳态窄脉冲展宽电路的详细过程和这种单稳态窄脉冲展宽电路的特点 ,给出了相应的时序仿真波形和计数器的VHDL语言设计。
The paper introduced a process of designing monostable pulse width cicuit with CPLD and the characteristic of the circuit. Emulation oscillogram and counter design with VHDL were given.
出处
《应用科技》
CAS
2001年第12期7-8,6,共3页
Applied Science and Technology
