3.75GHz 0.35μm CMOS1∶4静态分频器集成电路设计

3.75GHz1∶4 Static Frequency Divider IC Design using 0.35μm Standard CMOS Technology

给出了一个利用 0 35 μmCMOS工艺实现的 1∶4静态分频器设计方法。该分频器采用源极耦合场效应管逻辑电路 ,基本结构与T触发器相同。测试结果表明 ,当电源电压为 3 3V、输入信号峰峰值为 0 5V时 ,芯片可以工作在 3 75GHz,功耗为 78mW。

The design of a 3.75 GHz 1∶4 static frequency divider using 0.35 μm CMOS technology is given in this paper.The divider is designed in the Source Coupled Logic,with the structure being similar to the T filp flop.It is shown by tests and measurements that the chip can run at a high frequency of 3.75 GHz under a 3.3 V power supply with an input of 0.5V Vpp.Its power dissipation is 78mW.