摘要
本文提出了一种适于数据通路应用的快速可编程逻辑单元 .该单元采用功能增强的MUX结构 ,在配置为异或 同或 多路选择器 (XOR XNOR MUX)结构时 ,只用一个单元的开销就可实现一位全加器、基本乘法单元等适于数据通路应用的功能 .该单元还能实现全部 3输入逻辑和部分 4~ 7输入逻辑 ,也是一种满足通用逻辑应用的结构 .这种单元的组合逻辑部分只采用了 3个 2选 1多路选择器 (2 :1MUX)和两个功能增强的输入可反相编程的多路选择器(2 :1EMUX) ,有效地节省面积和提高了速度 .HSPICE模拟分析表明 ,在 5V、0 6 μm工艺条件下 ,该单元的最大时延小于0 6ns,进位时延小于 0 1ns.其性能。
Presents a high speed programmable logic cell for datapath,whose architecture consists of enhanced multiplexer.When the cell is configured for XOR XNOR MUX scheme,it can achieve the functions such as one bit full adder and base multiplier cell and so on for datapath application.It is also configured for all 3 input logic and some logic between 4 and 7 input,and used for general combinational logic.The cell is only made up of three 2:1 MUX and two enhanced 2:1 MUX inverted by programming,achieves fast speed and costs little chip area.The advantages of its speed and area are proved by simulation analysis with HSPICE.The larger propagating delay is less than 0 6ns and the carry chain delay is less than 0 1ns under 5V,0 6μs CMOS process.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2002年第2期180-183,共4页
Acta Electronica Sinica
基金
国家自然科学基金 (No .60 0 760 1 4 )
高等学校博士点专项基金 (No .2 0 0 0 0 2 4 62 3)