基于可编程逻辑器件的定时器设计

Design of a Timer Based on CPLD

介绍了用 EDA技术实现的 99分钟内定时。本系统基于 VHDL语言 。

It introduced the 99-minute inner timing based on EDA technology. The system is based on VHDL language and takes CPLD (Complex Programmable Logic Device) as its core.