三维多介质电容计算的有效方程组织方法

Efficient equation organization for 3-D multi-dielectric parasitic capacitance extraction

随着 VL SI电路集成密度急剧增长及特征尺寸不断缩小 ,快速准确地计算三维互连寄生电容已成为集成电路辅助设计中一个研究热点。提出一种有效的多介质直接边界元方程组织方法。该方法排列直接边界元方程组中的源点和变量 ,使系数矩阵非零元分布极有规律 ,通过最少的数组存储非零矩阵块 ,以达到加快方程迭代求解的目的。该方法可应用于任意复杂结构的三维寄生电容计算 ,对介质数目较多的虚拟多介质计算 。

In the VLSI (very large scale integration) circuit, with the feather size scaled down and the indensity increased, fast and accurate computation of 3 D interconnect capacitance is becoming very important to design of high performance IC (integrated circuit). An efficient approach is proposed to organize the linear equations produced by the multi dielectric direct BEM computation. The non zero elements are distributed regularly in the matrix, when the source points and variables are properly arranged. Then, the computational cost of the equation solution is markedly reduced by storing them in a few two dimensional arrays. The approach can be applied to any complex multi dielectric structure of a 3 D VLSI parasitic capacitor. The approach performs much better than existing approaches especially for the quasi multiple medium accelerating computation which has more medium blocks.