JAVA智能卡微处理器的设计与验证

Design and verification of a Java smart card processor

针对智能卡的应用特点 ,设计了一种流水线型 Java微处理器。使用一读一写的双口 RAM作为 Java堆栈 ,减小了存储资源的消耗。通过有限状态机对流水线的控制 ,在若干个时钟周期内完成了 Java智能卡虚拟机 (JCVM)的中等复杂指令的处理。提供了硬件陷阱机制 ,以支持 JCVM非常复杂和面向对象指令的软件仿真。整个设计实现了全部 16bit数据宽度的 JCVM指令和额外的扩展指令 ,用 VHDL 语言进行了行为仿真和寄存器传输级描述 ,Synopsys综合的结果为 1.3万等效门 ,在 10 MHz时钟频率下 ,通过了现场可编程门阵列的硬件验证。

A pipelined Java processor designed to process Java smart card applications utilizes a one read one write dual port RAM as a Java stack to reduce the consumption of hardware resources. Control of the pipeline stages by a finite state machine allows execution of moderately complex Java card virtual machine (JCVM) instructions within several clock cycles. It also provides a hardware trap to support software emulation of very complex and object oriented JCVM instructions. This processor implements all JCVM instructions with 16 bit data width and some extended instructions. The behavior and register transfer level models of this processor are described using VHDL. The design using Synopsys had about 13 thousand gates. A hardware prototype was constructed using field programming gate arrays and verified at 10 MHz frequency. This processor can meet the cost and speed requirements of current smart card applications.