一种用于HDTV集成解码芯片的I/O控制策略

A Efficient I/O Control Scheme for HDTV Decoder

数据的存取控制是系统集成芯片软硬件协同设计中的关键环节。许多文献都给出了对 ＭＰＥＧ—２ ＭＰ＠ＭＬ视频解码器的Ｉ／Ｏ控制策略，但是很少涉及如何有效地存取ＭＰＥＧ—２ＭＰ＠ＭＬ的数据，特别是如何控制包含系统层、视频和音频三个部分进行解码的集成解码芯片的数据输入输出。本文通过详细的分析和计算，结合不同类型数据传送的特点，提出了一种有效的用于这种集成解码芯片的Ｉ／Ｏ控制策略，在增加有限的芯片引脚的情况下，简化了数据输入输出的控制逻辑，降低了片上用于Ｉ／Ｏ控制的逻辑资源。

Data access is a key technology in software/hardware-codesign of SOC (System on chip). Many papers have presented I/O control scheme for MPEG-2 MP@ML video decoder, but few is concerned on MP@HL, especially for the decoder that include system layer, video and audio decodings. This paper presents a efficient I/O control scheme for this decoder, which is accomplished by simplifying their control logic through adding limited I/O pins.