多级逻辑面积优化设计方法

Design Approach of Multilevel Logic Optimization for Area

该方法应用于超大规模集成电路的设计过程。逻辑优化是这一过程中的重要步骤。经优化后产生主题图质量的好坏,直接影响到最后的设计结果。该文针对主题图面积的优化问题,提出了“多级逻辑面积优化”设计方法。该方法通过“逻辑等价变换”技术,达到进一步优化主题图面积的目的。

This method is used in the design of VLSI.The logic optimization is significant during the process.The sub-ject-graph which is obtained by logic optimization effects the final result of the design.This paper presents a new method named'multilevel logic optimization for area'which aims at the area of the subject-graph.Logic equivalent trans-formation technology is used in this method to reduce the area of the whole subject-graph.