期刊文献+

一个快速高效进行布线拥挤优化的总体布线器(英文) 被引量:2

A Fast and Efficient Global Router for Congestion Optimization
下载PDF
导出
摘要 设计实现了一个高效的线长模式下基于多处理机的并行总体布线器 .通过对非时延驱动模式下串、并行算法的总运行时间和求解时间的比较 ,表明该并行算法能够在保证求解质量无明显变化的前提下大大加快总体布线算法的求解速度 .同时 。 An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2002年第2期136-142,共7页 半导体学报(英文版)
基金 国家自然科学基金 (No.60 0 760 16) 国家 973重点基础研究发展规划项目(No.G-19980 3 0 40 3 ) 中国博士后科学基金 (No.[2 0 0 0 ] 2 3 )资助项目~~
关键词 总体布线器 布线 拥挤优化 总体布线图 并行算法 集成电路 global routing congestion optimizing global routing graph (GRG) parallel algorithm
  • 相关文献

参考文献6

二级参考文献29

  • 1洪先龙.一种以电性能优化为目标的Steiner树算法[J].计算机学报,1995,18(4):266-272. 被引量:5
  • 2[1]A.L.Fishburn and H.T.Kung,Synchronous Large Systolic Arrays,Proc.of SPIE,1982,45~52.
  • 3[2]M.Jackson,A.Srinivasan,and E.S.Kuh,Clock Routing for High Performance ICs,Proc.of 27th ACM/IEEE DAC,1990,573~579.
  • 4[3]A.B.Kahng,J.Cong and Robins,High-Performance Clock Routing Based on Recursive Geometric Matching.Proc.of 28th ACM/IEEE DAC,1991,322~327.
  • 5[4]R.S.Tsay,Exact Zero Skew,Proc.of IEEE ICCAD,1991,336~339.
  • 6[5]Q.Zhu and W.W.-M.Dai,Perfect-Balance Planar Clock Routing With Minimal Path-Length,Proc.IEEE Int.Conf.CAD,Nov.,1992,473~476.
  • 7[6]T.H.Chao,Y.C.Hsu and J.M.Ho,Zero Skew Clock Net Routing Proc.of 29th ACM/IEEE DAC,CA,1992,518~523.
  • 8[7]M.Edahiro,A Clustering Based Optimization Algorithm in Zero Skew Routing,Proc.of 30th ACM/IEEE DAC,TX,1993,612~616.
  • 9[8]M.Edahiro,Minimum Skew and Minimum Path Length Routing in VLSI Layout Design,NEC RES.DECEL.Oct.,1991,569~575.
  • 10[9]T.H.Chao,Y.C.Hsu and J.M.Ho,Zero Skew Clock Net Routing,Proc.ACM/IEEE DAC,1992,518~523.

共引文献30

同被引文献6

引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部